The CXP Host IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The CXP Host IIP can be implemented in any technology.

The CXP Host IIP core supports the CXP 1.1/1.1.1/2.0 specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture -AHB,AHB-Lite,APB,AXI, AXI-Lite, Tilelink,OCP,VCI,Avalon,PLB,Wishbone or custom buses.