The SAS Initiator IP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The SAS Initiator IP can be implemented in any technology.

The SAS Initiator IP core is fully compliant with Serial ATA SCSI 5.0 Specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, VCI, Avalon PLB, Wishbone or custom buses.

The SAS Initiator IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The SAS Initiator IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.