The TS5 Slave Controller IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The TS5 Slave Controller IIP can be implemented in any technology.

The TS5 Slave Controller IIP core supports JEDEC TS5111, TS5110 specifications. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, Wishbone, Avalon, PLB, Tilelink, Wishbone or custom buses.

The TS5 Slave Controller IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The TS5 Slave Controller IIP is validated using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.